1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor, and particularly to a heterojunction bipolar transistor having device size defined by ion implantation.
2. Description of the Related Art
With the progress of industries in these days, there are continuously increasing demands for a computer of the ultra high and ultra large type, for a communication system of large capacity, and for a vehicular communication system of high frequency range. As an ultra high speed device suitable for such usages, heterojunction bipolar transistors formed of compound semiconductors, such as GaAs and InP are drawing attention and have been developed actively at present.
In order to allow these transistors to operate in a high speed, it is necessary to reduce parasitic capacitances, and thus to minimize the element sizes of the device, especially emitter size. A method utilizing an ion implantation is known as a method for minimizing and defining the emitter size. This method is to implant ions, such as B.sup.+, H.sup.+, and 0.sup.+, into an area from the outside of a mesa to a marginal portion of a semiconductor layer for forming the emitter region in the mesa. By virtue of this, the marginal portion of the semiconductor layer, and a marginal portion of a semiconductor layer for forming a base region are changed to have high resistances, whereby the emitter length is defined in the direction of leading an emitter electrode.
FIG. 1A shows a plan view of a conventional heterojunction bipolar transistor in which emitter size is reduced by ion implantation. FIG. 1B shows a cross sectional view along line IB--IB in FIG. 1A. In FIGS. 1A and 1B, reference symbol 10 denotes an i-type (intrinsic semiconductor, semiinsulative) substrate; 11, an n.sup.+ -type collector contact layer; 12, an n-type collector layer; 13, a p.sup.+ -type base layer; 14, an n-type emitter layer; 15, an n.sup.+ -emitter contact; 16, a high resistant region implanted with B.sup.+ ions; 22, a base electrode; 23, an insulating layer; and 24, an emitter electrode. In this structure, part of the interface 28 of the ion implanted region 16 is located inside a mesa 27, so that part of the emitter layer 14 is changed to have a high resistance, whereby the emitter length is defined in the direction of leading an emitter electrode.
In the case of defining emitter length by well known wet etching methods, an isotropic wet etching is apt to reduce pattern accuracy of the emitter mesa, while an anisotropic wet etching is apt to form reverse taper on the sides of the emitter mesa thereby cutting off interconnections for leading an electrode. Therefore, the above described method for defining the emitter length by ion implantation as shown in FIGS. 1A and 1B was considered to be an advantageous technique for manufacturing a high speed device.
However, recently, it has been found that this method has a substantial defect in the reliability of the resultant device. As a result of experiments of accelerative degradation under high temperature and electric current flowing conditions conducted by the inventors, it has been found that a device having a emitter length defined by ion implantation is apt to increase its on-voltage (base-emitter voltage when a predetermined collector current starts to flow), and thus degrade its characteristics. This is attributed to base impurities, such as Be, C, Zn, Mg, Si, or Sn, being abnormally diffused into the emitter region which differs in band gap energy from the base region (Reference material; Shigaku Giho Vol. 91, No. 423, ED91-163, MW91-146, ICD91-189).
As mentioned above, when emitter size is defined by wet etching method, reduction of the accuracy of pattern and cutting of interconnections for leading electrode are caused and device reliability is reduced. Also, when the emitter size is defined by ion implantation, there is a problem of on-voltage changes.